DFT Engineer (Entry / Mid / Senior)

About the role

We are looking for a DFT Engineer to join our ASIC test team, responsible for end‑to‑end DFT architecture, implementation and debug across pre‑silicon and post‑silicon phases. The role works cross‑functionally to ensure high test coverage, optimized test cost and scalable solutions for complex SoCs and multidie designs.

Key responsibilities

• Define and drive DFT architecture and methodologies at block, chip and package levels.
• Insert, verify and validate scan chains, compression, ATPG patterns and meet coverage targets for sign‑off.
• Design and implement test clocking architectures, including OCC for multi‑clock SoCs.
• Support memory test, repair and configuration flows (MBIST, BISR, OTP/eFUSE) in both pre‑ and post‑silicon phases.
• Implement Boundary Scan (BSCAN/EBSCAN) and multidie DFT architectures (chiplet, 2.5D, 3D‑IC).

Required profile

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• Hands‑on experience with Mentor Tessent tools (TestKompress, SSN, OCC, IJTAG).
• Strong understanding of DFT fundamentals: scan, compression, ATPG, fault simulation, MBIST/LBIST.
• Experience with multidie/chiplet test architectures and IEEE standards (JTAG, IJTAG, IEEE1500).

Required skills

• Mentor Tessent (TestKompress, SSN, OCC, IJTAG)
• Scan chain insertion, compression, ATPG, fault simulation
• MBIST/LBIST, memory test and repair flows
• Test clocking, OCC, STA interactions
• PDK, synthesis and physical design flow knowledge
• Scripting: TCL, Perl, Python, Shell
• Verilog/VHDL, simulation and waveform debugging
• IEEE 1149, IEEE 1687, IEEE1500 standards