Senior SoC/ASIC Physical Design Engineer

About the role

We are looking for a Senior SoC/ASIC Physical Design Engineer to lead the implementation of cutting‑edge system‑on‑chip designs. In this role you will develop and refine design flows, methodologies and automation scripts to deliver high‑performance, low‑power silicon.

Key responsibilities

• Perform partition synthesis, floorplanning, power‑grid generation, placement, routing and sign‑off checks (timing, noise, electromigration, voltage drop, logic equivalence).
• Develop and improve physical design methodologies and automation scripts for each implementation step.
• Collaborate closely with ASIC design teams to define timing, power and area targets and evaluate RTL trade‑offs.
• Troubleshoot and resolve design, timing and congestion issues, driving solutions through to execution.
• Run, debug and close sign‑off issues in STA, noise analysis, physical verification and power integrity.

Required profile

• 5+ years of ASIC or physical design flow development experience.
• Self‑driven with a can‑do attitude and a passion for learning new technologies.
• Strong communication skills and ability to work with multidisciplinary teams across time zones.
• Commitment to producing high‑quality code and documentation.

Required skills

• ASIC physical design flow: synthesis, floorplanning, place‑and‑route, STA, formal verification, CDC, power analysis.
• Experience with voltage scaling techniques (SVS, DVFS) and SRAM split‑rail implementation.
• Proficiency with Synopsys EDA tools and understanding of underlying algorithms.
• Scripting in Python, Tcl, Perl, Bash/csh and Makefile.
• Deep knowledge of deep‑sub‑micron FinFET and CMOS physics, standard‑cell libraries and power dissipation mechanisms.
• Familiarity with DFT/Scan/MBIST/LBIST and their impact on physical design.