ASIC Microarchitect – Digital Design Engineer

About the role

We are seeking an ASIC Microarchitect to design and implement cutting‑edge digital systems, System‑on‑Chips (SoCs) and high‑performance RISC‑V cores. You will work closely with system, software, hardware and physical implementation teams to create microarchitectures that balance power, performance and area.

Key responsibilities

• Architect, design and implement high‑performance, low‑power ASIC and SoC digital designs using industry‑standard EDA tools.
• Collaborate with the physical implementation team to run power, performance and area experiments and optimise trade‑offs.
• Work with performance‑modelling teams to model functionality and explore optimisation opportunities.
• Engage with systems and software groups to ensure seamless integration from design through verification.
• Drive technical innovation, especially within the RISC‑V ecosystem, and contribute to design and code reviews.

Required profile

• Bachelor’s degree in Computer Engineering or Electrical Engineering.
• 5+ years of experience in microprocessor architecture with successful implementations.
• Familiarity with processor architecture, memory and cache subsystems, on‑chip interconnects, Network‑on‑Chip, AXI and RISC‑V (strong plus).
• Strong programming skills in Python, C/C++, Chisel or assembly language.
• Experience with fixed‑point and floating‑point arithmetic and datapath design is desirable.
• Passion for learning, high‑quality code and documentation, and excellent communication skills.

Required skills

• Python
• C/C++
• Chisel
• Assembly language
• RISC‑V architecture
• Processor architecture
• Memory and cache design
• On‑chip interconnects / AXI
• Fixed‑point and floating‑point arithmetic
• Datapath design
• Industry‑standard EDA tools